Low Power Optimization for Edge Computing Artificial Intelligence Chips
Last Updated Date 2023-11-27
- Course Sorts:Moe Talent Cultivation Project for Advanced IC Design ／ 112年度
- Course Introduction:
- Course Introduction Video:
Edge AI Chip Power Optimization (Algorithm-level)
a. Power optimization in FinFET process
b. Introduction to Edge AI applications
c. Quantization, Retraining methods, and Accuracy trade-off
d. Memory power optimization
Edge AI Chip Power Optimization (EDA flow with Generic process)
a. Clock Gating, minPower Components, and RTL-code writing style
b. Simulation and Power Analysis (RTL and Gate-level)
a. Power optimization in FinFET process
b. Introduction to Edge AI applications
c. Quantization, Retraining methods, and Accuracy trade-off
d. Memory power optimization
Edge AI Chip Power Optimization (EDA flow with Generic process)
a. Clock Gating, minPower Components, and RTL-code writing style
b. Simulation and Power Analysis (RTL and Gate-level)
Course Attachments
Update Time 2023-11-27 15:11:39
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