SELECT t.* FROM class_faq t WHERE t.class_id = '236' AND t.online = 'Y' AND t.verify = 'Y' ORDER BY t.make_time ASC The Design and Implementation of a RISC-V Multi-Core Processor-ATP Course Database System｜Ministry of Education Talent Cultivation Project for Intelligent Chip and Design Allience

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The Design and Implementation of a RISC-V Multi-Core Processor

Course Application

Last Updated Date 2025-04-24

Course Sorts:Moe Talent Cultivation Project for Advanced IC Design ／ 113年度
Course Introduction:

Basics of RISC-V processors

RISC 架構概念與 RISC-V 簡介

RISC-V Instruction Set Architecture

指令格式與分類
基本組合語言實作與模擬

Design and Implementation of Single-core RISC-V Processors

單核心架構介紹與設計

Design and Implementation of Dual-Core RISC-V Processors

多核心架構與通訊機制之介紹與設計

Course Introduction Video:

Course Attachments

Update Time 2025-04-21 19:47:10

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Lecture

晶片前瞻技術模組教材-113-RISC-V 多核處理器之設計及其實作-講義-1.rar(15.01 MB)

Update Time 2025-04-21 19:47:10

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Practice

晶片前瞻技術模組教材-113-RISC-V 多核處理器之設計及其實作-實作-1.rar(172.27 MB)

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Course Recording 1

晶片前瞻技術模組教材-113-RISC-V 多核處理器之設計及其實作-課程錄影-1.mp4(827.01 MB)

Update Time 2025-04-21 19:47:10

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Course Recording 2

晶片前瞻技術模組教材-113-RISC-V 多核處理器之設計及其實作-課程錄影 2-1.mp4(470.15 MB)

Update Time 2025-04-21 19:47:10

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Course Recording 3

晶片前瞻技術模組教材-113-RISC-V 多核處理器之設計及其實作-課程錄影 3-1.mp4(733.64 MB)

Course Q&A